1. Field of the Invention
The present invention relates to a subscriber (so-called host) of a communication system. The subscriber has a microprocessor, at least two communication controllers and a peripheral bus. The microprocessor is connected to the communication controllers via the peripheral bus and is connected via the communication controllers to each communication link of the communication system over which messages are transmitted.
The present invention also relates to a communication controller (CC) of the subscriber (so-called host) of a communication system. The subscriber has a microprocessor, the communication controller, optionally other communication controllers and a peripheral bus. The communication controller is in turn connected to the microprocessor via the peripheral bus and is also connected to a communication link of the communication system over which messages are transmitted.
Finally, the present invention also relates to a method for implementing a gateway functionality within a subscriber (so-called host) of a communication system. The subscriber has a microprocessor, at least two communication controllers and a peripheral bus. The communication controllers are connected on the one hand to the microprocessor via the peripheral bus and on the other hand each is connected to a communication link of the communication system over which messages are transmitted.
2. Description of Related Art
Networking of control units, sensors and actuators with the help of a communication system and a communication link designed as a bus system has increased drastically in recent years in modern vehicles as well as in mechanical engineering, in particular in the machine tool area and in the area of automation. Synergistic effects due to the distribution of functions to a plurality of control units may then be achieved. One speaks here of distributed systems. Communication among various subscribers takes place increasingly via a communication system designed as a bus system. Communication traffic on the bus system, access and receiving mechanisms as well as error processing are regulated via a protocol.
The FlexRay protocol is a known protocol for this purpose and is currently based on the FlexRay protocol specification v2.0. The FlexRay protocol defines a rapid deterministic and error-tolerant bus system, in particular for use in a motor vehicle. Data transmission according to the FlexRay protocol takes place according to a time division multiple access (TDMA) method. Data transmission via the communication link takes place in regularly recurring transmission cycles, each being subdivided into multiple data frames, also known as time slots. Fixed time slots in which the subscribers have exclusive access to the communication link are assigned to the subscribers and/or to the messages to be transmitted. The time slots are repeated in the defined transmission cycles, so the point in time at which a message is transmitted over the bus may be predicted accurately in advance and bus access is provided deterministically.
To optimally utilize the bandwidth for the message transmission on the bus system, FlexRay divides the transmission cycle, also referred to as cycle or bus cycle, into a static part and a dynamic part. The fixed time slots are in the static part at the beginning of a bus cycle. In the dynamic part the time slots are issued dynamically. Exclusive bus access therein is then made possible for only a short period of time, for one or more so-called minislots. Only if bus access takes place within a minislot is the time slot lengthened by the required time. Bandwidth is thus used only when actually needed.
FlexRay communicates via two physically separate lines of the communication link at a data rate of max. 10 Mbit/s each (10 Mbaud). A bus cycle is completed every 5 ms, or even every 1 ms or 2.5 ms with many communication systems. The two channels correspond to the physical layer, in particular in the OSI (open system architecture) layer model. The two channels are mainly for redundant and therefore error-tolerant transmission of messages but may also transmit different messages, which would then double the data rate. However, FlexRay may also be operated at lower data rates.
To implement synchronous functions and to optimize the bandwidth through small intervals between two messages, the subscribers, i.e., the distributed components in the communication network, require a common time base, the so-called global time. For clock synchronization, synchronization messages are transmitted in the static part of the cycle, local clock time of a subscriber being corrected with the help of a special algorithm in accordance with the FlexRay specification, so that all local clocks run synchronized with a global clock.
A FlexRay subscriber, which may also be referred to as a FlexRay network node or host, contains a subscriber processor or a host processor, a FlexRay controller or communication controller and, in the case of bus monitoring, a so-called bus guardian. The subscriber processor then supplies and processes all the data transmitted over the FlexRay communication controller and the FlexRay communication link. For communication in a FlexRay network, messages and/or message objects having up to 254 data bytes, for example, may be configured.
For coupling a FlexRay communication link over which messages are transmitted to a FlexRay subscriber, German patent application document DE 10 2005 034 744, describes the use of a FlexRay communication module which is connected via a subscriber interface to the subscriber and via another link to the communication link. For transmission of messages between the subscriber and the communication link, a structure for saving the messages is provided in the communication module. The transmission is controlled by a state machine. The FlexRay communication module may be an integral component of the FlexRay communication controller or may be designed as a separate component.
An interface module composed of two parts is provided in the communication module, one submodule being independent of the subscriber and the other submodule being subscriber-specific. The subscriber-specific or customer-specific submodule, also known as a customer CPU interface (CIF), connects a customer-specific subscriber in the form of a subscriber-specific host CPU to the FlexRay communication module. The subscriber-independent submodule, also known as the generic CPU interface (GIF), is a generic, i.e., general CPU interface over which different customer-specific host CPUs may be connected to the FlexRay communication module via appropriate subscriber-specific submodules, i.e., customer CPU interfaces (CIFs). This allows problem-free adaptation of the communication module to different subscribers because, depending on the subscriber, only the subscriber-specific submodule need be varied, whereas the subscriber-independent submodule and the rest of the communication module may always be designed the same. Thus, with the help of the communication module, a standard interface is obtained for connecting any FlexRay subscribers to a FlexRay communication link, such that the interface may be flexibly adapted to subscribers of any type or design by simply varying the subscriber-specific submodule. The submodules may also be implemented in software within the one interface module, i.e., each submodule as a software function.
The state machine in the FlexRay communication module may be hard-wired in the hardware. Alternatively, the state machine in the communication module may also be freely programmable by the subscriber via the subscriber interface.
According to the related art, the message memory in the FlexRay communication module is preferably embodied as a single-ported RAM (random access memory). This RAM memory saves the messages or message objects, i.e., the actual useful data together with configuration data and status data. The precise structure of the message memory in the known communication module is described in the German patent application document DE 10 2005 034 744 which was cited above.
According to the related art, within the subscriber the microcontroller, which includes the microprocessor (so-called host CPU), a memory (e.g., random access memory RAM) and a core bus between the microprocessor and the memory, is connected to the peripheral bus as the so-called master via a passive interface and an active interface. The microcontroller is only able to receive commands and data from other subscribers of the peripheral bus via the passive interface. Via the active interface the microcontroller itself may send data and commands to other subscribers of the peripheral bus. Connection of a subscriber to the peripheral bus via a passive interface is equivalent to connecting the subscriber as a so-called slave. A connection of a subscriber via an active interface corresponds to a connection of the subscriber as a so-called master. In a known communication system, a communication controller is connected as a so-called slave to the peripheral bus via a passive interface.
The communication controllers establish the connection of the subscriber to one or more communication links (e.g., CAN, TTCAN, MOST, FlexRay, ByteFlight, etc.). Each has a message memory in which messages newly received from the communication link are stored and messages to be sent on the communication link are read out. The microprocessor (host CPU) may access the saved message objects via the passive interface of the communication controller.
The microprocessor configures, monitors and controls the communication controller. The microprocessor reads out received messages, evaluates them, calculates new messages and ensures the writing of the messages for sending over the communication link. For data transmission within the subscriber, the microprocessor transmits data word by word out of the communication controller into the memory of the microcontroller. At the high clock rates of the microprocessor customary today, multiple waiting cycles occur during which the microprocessor waits for the end of the data transmission and is unable to pursue any other tasks.
In simple gateway operations, it is often necessary only to read out the received data from a communication controller of the subscriber and to write it to one or more other communication controllers of the subscriber for sending. If no DMA (direct memory access) controller is used, the microprocessor (the host CPU) transfers data word by word out of the communication controllers into a memory element assigned to the microprocessor or into a memory element internal to the CPU to process it, if necessary, and then copy it to the appropriate communication controller. At the high clock rates of the microprocessor (the host CPU) customary today, several waiting cycles occur during which the microprocessor is blocked and is unable to perform any other tasks.
The microprocessor configures, checks, and controls the at least one communication controller and/or the logic circuit contained therein as well as the configuration data of the active interface. The microprocessor reads out and evaluates and/or processes message objects already received in the message memory of the communication controller and automatically copied into the memory element of the microprocessor, calculating new memory objects and storing them in the memory element of the microprocessor. In addition, information is transmitted to the appropriate communication controllers so that they are able to transfer the up-to-the-minute data out of the memory element of the microprocessor to their own message memory.
It is also known that, for relieving the burden on the microprocessor of the microcontroller of a subscriber of the communication system, a DMA controller may be connected to the peripheral bus via a passive interface and an active interface as a so-called master. The DMA controller may perform a data transfer between the memory element of the microcontroller and the communication controller. It is configured and initialized by the microprocessor (host CPU) for this purpose. The DMA controller then transfers data word by word out of the communication controller into the memory element of the microcontroller or—if this function is supported—directly between the communication controllers. The end of data transfer is reported to the microprocessor via an interrupt, whereupon the microprocessor restarts the process for the next message. Processing of interrupts generates a large number of CPU commands, which ties up a large portion of the computation and memory resources of the microprocessor. In addition, the possible jitter (uncertainty with regard to the execution duration over time) of interrupted software tasks increases due to the frequent interrupts.